ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years

Cisco is hiring an ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years in Bengaluru, India. Level rates it ; you can apply on Cisco.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include System Verilog, Verilog and UVM.
Level classifies it as a lead role.
Level lists 1,400+ other open roles at Cisco.

AI in this role

Lead ASIC design verification for core networking silicon using Verilog, SystemVerilog, and UVM methodologies.

System VerilogVerilogUVM

asic-verificationtestbenchrtlgate-level-simulation

Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by crafting, developing and testing some of the most sophisticated ASICs being developed in the industry. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle.

Your Impact

You will contribute to developing Cisco’s progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include:

• Architect block, cluster and top-level DV environment infrastructure.

• Develop DV infrastructure from scratch.

• Maintain and improve existing DV environments.

• Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus.

• Ensure complete verification coverage through implementation and review of code and functional coverage.

• Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist.

• Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance.

• Support testing of design in emulation.

• Lead all aspects of and manage the ASIC bring-up process.

Minimum Qualifications

• Bachelor’s degree or master’s Degree in equivalent experience in EE, CE, or other related field.

• 10+ years of related ASIC design verification experience.

• Proficient in ASIC verification using UVM/System Verilog.

• Proficient in verifying sophisticated blocks, clusters and top level for ASIC.

• Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.

• Scripting experience with Perl and/or Python.

Preferred Qualifications

• Experience with Networking ASICs would be an advantage

• Experience with Forwarding logic/Parsers/Buffer management/Arbitration and scheduling

• Experience with Veloce/Palladium/Zebu/HAPS.

• Formal verification (iev/vc formal) knowledge.

• Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, IPv4/6, TCP).

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Disclaimer

To ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:

be in direct response to an application you have submitted through the company career site
begin with screening or an interview
originate from a Cisco email address, and
be conducted across email, phone, or WebEx

Cisco will never make a job offer without conducting an interview process or ask you for money in any way. If you have been requested to apply for a role or have received an offer from a site other than https://careers.cisco.com or cisco.wd5.myworkday.com, do not provide any personal identifying information, including your Aadhaar or other personal identifying number, birth certificate, banking information, driver's license, or passport.

If you are the target of a recruiting scam, consider filing a report with your local law enforcement authorities. Cisco bears no responsibility, and cannot be held liable, for any claims, damages, expenses, or other inconvenience resulting from or in any way connected to recruiting scams.

How we rate this

ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years at Cisco rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years is an open job at Cisco.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in Bangalore, India.
The job was posted on September 3, 2026.
Seniority: lead.
Applications are handled by Cisco. Apply on Cisco

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic VerificationTestbenchRtlGate Level SimulationSystem VerilogVerilogUVM

Questions you could be asked

Tell me about a project where asic verification was part of your work. What did you do?
Tell me about a project where testbench was part of your work. What did you do?
Tell me about a project where rtl was part of your work. What did you do?
Tell me about a project where gate level simulation was part of your work. What did you do?
Walk me through how you've used System Verilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Asic Verification, Testbench, Rtl, Gate Level Simulation, and System Verilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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