CPU DFT Manager

Intel is hiring a CPU DFT Manager in Bengaluru, India. Level rates it ; you can apply on Intel.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
Tools and skills the posting cites include Spyglass Dft, Rtl and Ate.
Level classifies it as a lead role.
Level lists 826 other open roles at Intel.

AI in this role

Manage and technically guide a Design for Test team focused on X86 CPU DFT design, verification, and debugging.

Spyglass DftRtlAte

dft-designcpu-architecturesilicon-validationchip-design

Job Details:

Job Description:

Key Responsibilities: Leadership and Management: -Manage and technically guide a high-performing DFT team focused on X86 CPU DFT design and validation. -Develop detailed execution plans for parallel activities across multiple projects and ensure timely, high-quality delivery. DFT Design and Verification: -Implement JTAG, Memory BIST, and Memory Repair (BIRA/BISR) circuitry using industry-standard tools. -Drive DFT verification for features such as scan, arrays, and DFD using RTL simulations and emulation. -Create plans and tests for validating portions of complex microarchitecture using written specs, RTL code, and other test guides. Technical Problem Solving: -Debug failures to root cause and learn architecture/microarchitecture deeply. -Collaborate with post-silicon/manufacturing teams on ATE, debugging and resolving issues. -Cross-Functional Collaboration: -Work closely with global stakeholders to address DFT challenges and improve product quality. -Ensure alignment of timelines and deliverables across sites.

Qualifications:

• 10+ years of experience in DFT domain at IP or SoC level. • 5+ years of experience managing and leading teams. • Strong knowledge and experience in Spyglass DFT. • Hands-on skills in implementing JTAG, Memory BIST and Memory Repair (BIRA/BISR) circuitry. • Expertise in DFT Design and verification using RTL simulations and emulation. • Good understanding of timing constraints and DFT mode timing analysis. • Proficiency in RTL coding and shell scripting. • Experience working with post-silicon/manufacturing teams on ATE, including debugging and issue resolution. • Experience with X86 CPU architecture and microarchitecture. • Familiarity with advanced process nodes and hierarchical DFT strategies. • Strong communication and leadership skills for cross-site collaboration.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

CPU DFT Manager at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

CPU DFT Manager is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in India, Bangalore.
The job was posted on July 7, 2026.
Seniority: lead.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Dft DesignCpu ArchitectureSilicon ValidationChip DesignSpyglass DftRtlAte

Questions you could be asked

Tell me about a project where dft design was part of your work. What did you do?
Tell me about a project where cpu architecture was part of your work. What did you do?
Tell me about a project where silicon validation was part of your work. What did you do?
Tell me about a project where chip design was part of your work. What did you do?
Walk me through how you've used Spyglass Dft in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Dft Design, Cpu Architecture, Silicon Validation, Chip Design, and Spyglass Dft. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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